Today, the Analog Components, on an average, contribute to 60%-70% of the real estate on the silicon. In order to spin these silicon out successfully, there needs to be a very strong Analog IP expertise, including the hardcore Analog circuit design expertise, Integration knowledge and Strong benchmarking capabilities. Now-a-days, these forces drive silicon based product solution companies towards having a top class in-house Analog, RF and MEMS team to ensure seamless and successful chip development cycle.
We, at ORLYSEMI, believe that Analog is the future of the silicon, also the solution to many problems of exponentially scaling up digital world, as seen today. So we are building the strong Analog expertise internal to the company. With us, there is a mixed blend of Analog Circuit Design as well as Layout Design capabilities in the areas of IP design, Foundation IP, RF design etc. Another area of focus is the Transistor level design of Analog and mixed-signal circuits for smart power stages and other low power management functions. The team has the experience of handling and owning the complete IP design from scratch in advanced technology nodes adhering to any of the design specification. The team has worked for customers in wireless, automotive, connectivity and IoT markets.
We work with marketing, sales, application engineers and customers to help define new products and support our customers in the following areas
Analog IP Circuit Design and Layout
Foundation IP Design, Layout and Characterization
Analog Test Chip support
Analog verification support
Full chip signoff support (LVS, DRC, EM, ESD, Antenna, DFM)
Technology experience on varying process nodes from 130nm to 4nm
Proficiency in working with tools from Cadence, Synopsys, Intel, Mentor
Wide range of memory with variety of architecture with top semiconductor companies has been done before. These includes Multi port memories, SRAM, Memory compilers, Register files & custom memories on cutting edge technologies.
FINFET 22nm – 10nmFDSOI 22nmPLANAR 180, 90, 286T SRAM bit-cell on logic DRC6T SRAM bit-cell memory array development1T ROM Compiler Developments RAM Compiler Development ROM Compiler Development Multi-port memory development Ultra-High Density, Dual Port, 8T SRAM development ARF, Self-Time, Centre Decoding, Multi Bank, Power Gating, Self-Test Techniques Memory Compiler FULL RANGE Characterization for multiple technologies Critical Path, Timing, Set-up & Hold Matching Circuit design development Fine tuning in Memory Compilers ARF, SELFTIME, DUALPORT, UHD, HDSP, POWER GATING, BIST
Our team has in-depth expertise on variety of IPs such as SerDes (10, 16, 30 & 56 Gbps), DDRphy, USB 2.0, MIPIphy and Power management. We have also handled expanded portfolios of Data converters, clock circuits such as PLL, DLL & oscillators, Regulators, Bias, Bandgap references, Temperature sensors, UVLOs etc in almost all leading foundries at technologies varying from 500nm BCD to 7nm Finfet. Multiple full chip and IP level tape out has been successfully done with first pass silicon. What sets us unique is that the knowledge gained is shared among other team members across sites to close the skill gap at any experience level.
In the past, our team has delivered multiple std cell libraries at 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16FF, 14nm, 10nm etc. with leading foundries. These libraries include High performance, High density, 11T, 9T, 7.5T, 6T design. We are also expert when it comes to migration of libraries to latest technologies.
Our team has delivered IO layout from 250nm to 16nm technologies. These includes GPIOs, LVCMOS, LVTTL, LVDS, DDR etc. with Analog/Power ring. ESD requirements for HBM, MM, CDM were taken care.
FDSOI 22nm – 10nm
PLANAR 180, 90
GPIO library
ESD PROTECTION
Clampers
Power Supply Cells
ALL BASIC ANALOG BLOCKS
Physical Implementation business unit within ORLYSEMI is one of the seasoned groups within the company, housing a highly experienced world-class team that has churned out multiple first pass silicon’s in advanced technology nodes for varied class of customers across wireless, automotive, connectivity, IoT markets. This team has the experience of taking a design from early premature RTL stage to supplying end silicon’s volumes to customers.
The team has worked on cutting edge technologies, designs and have been innovative in their offerings for each and every customer. The group has been constantly upgrading their knowledge base and can support customers in the following areas.
Silicon defects form a costly pill for any semiconductor product company and smartly identifying these early on in the product life cycle is a silver bullet. Murphy’s law states that “Anything that can go wrong will go wrong”, hence the Design Verification Solutions are to be state-of-the-art in nature and should be carefully crafted to perceive the hidden bugs.
The Design Verification business unit within ORLYSEMI believes in working towards covering all the functional, code coverage while continuously improvising the IP, Sub-System and System Level Verification Environment. Our experienced team has a robust verification environment and our unique verification methodologies can aim at achieving zero defect silicon.
We provide support in the following areas.
Maximum Coverage, Low DPPM, Minimum Cost and Improved Yield are the key performance indicators for any successful chip design company to master the art of DFT.
At ORLYSEMI we have a highly skilled and experienced team rendering services both in Front End and Backend DFT. Our primary focus is to provide silicon with least defects and optimized test time which in turn reduce the cost. Our DFT methodology provides a complete solution including MBIST, regular scan, AC scan, scan compression, boundary scan (JTAG), power aware test and ATPG, to achieve limit tending to 100% test coverage. We have been supporting customers across the globe on the whole spectrum of DFT flow from test architecture definition all the way to silicon bring up.
As a unit we offer our services in the following key areas.
Design For Test
New Product Introduction (NPI) Test Services
Product Qualification Test Services
Production Test Service
Tester tools capability
Shorter Time to Market is one of the most critical success factors of any Semiconductor company. So the real challenge is to reduce the Chip Development TAT by squeezing and/or parallelising various stages associated with the entire Chip Development Cycle and PSV plays a key role here. Even with very advanced Pre-silicon verification tools, Post Silicon Validation (PSV) is one of the most crucial steps in ensuring the functional correctness of the chip design. For the complex designs of today, traditional methods for PSV will be very time consuming but these measures are unavoidable. Applying software validation techniques in PSV is the key to solving the puzzle. This can provide significant reduction in validation schedule while also improving and monitoring the coverage requirement.
We consider this as an art more than just a technology skill. At ORLYSEMI we combine our expertise in the whole gamut of silicon realization to provide our customers with a whole spectrum of silicon validation services. We always aim to reduce the schedule and cost for silicon validation while ensuring required functional coverage is achieved.
Following are our Key Services
Functional validation
Power and Performance validation
Board Bring up & Automation
Tool Expertise
Pre-Silicon Environments
Post-Silicon Environments
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